Author:
Hosali Sharath,Smith Greg,Smith Larry,Vitkavage Susan,Arkalgud Sitaram
Reference41 articles.
1. Lo WC, Chen YH, Ko JD, Kuo TY, Chien CW, Chen YC, Chen WY, Leu FJ, Hu HT (2005) Development and characterization of low cost ultrathin 3D interconnect. ERSO/ITRI, Taiwan. Proceedings of the 2005 Electronic Components and Technology Conference, IEEE, pp 337–342
2. Miller WD, Gassman RA, Keicher DM (1993) Laser drilling of vertical vias in silicon. Sandia Report SAND93-1772, UC-704 for Unlimited Release
3. Flamm DL (1990) Mechanisms of silicon etching in fluorine and chlorine-containing plasmas. University of California, Berkeley, Pure Appl Chem 62 (9):1709–1720
4. Rosli SA, Aziz AA, Hamid HA (2006) Characteristics of RIE SF6/O2/Ar plasmas on n-silicon etching. Nano Optoelectronics Research and Technology Laboratory, Universiti Sains Malaysia, Proceedings of the International Conference on Semiconductor Electronics 2006, IEEE, Kuala Lumpur, Malaysia, pp 851–855
5. Figueroa RF, Speisshoefer S, Burkett SL, Schaper L (2005) Control of sidewall slope in silicon vias using SF6/O2 plasma etching in a conventional reactive ion etching tool. University of Arkansas, Fayetteville, AR, J Vac Sci Technol B 23(5):2226–2231
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Through Silicon Vias for 3D Integration—A Mini Review;Interconnect Technologies for Integrated Circuits and Flexible Electronics;2023-09-22
2. Die singulation technologies for advanced packaging: A critical review;Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena;2012-07
3. Development of flip-chip interconnections of photodetector readout circuit (ROIC);2010 11th International Conference on Electronic Packaging Technology & High Density Packaging;2010-08