1. Li, X.-Y. et al., “An effective method of characterization poly gate CD variation and Its impact on product performance and yield”, Proc. Int. Symp. Semicond. Manuf., 2003, 259–262.
2. Nagase, M.; Tokashiki, K. “Advanced gate etching for accurate CD control for 130-nm node ASIC manufacturing”, 2004 17(3), 281–285.
3. Schellenberg, F. “A little light magic [optical lithography]”, Spectrum IEEE, 2003, 40(9), 34–39.
4. Asenov, A.; Kaya, S.; Brown, A.R. “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness”, Electron Devices, 2003 50(5), 1254–1260.
5. Asenov, A. “Random dopant induced threshold voltage lowering and fluctuations in sub 0.1 micron MOSFETs: A 3D ‘atomistic’ simulation study,” IEEE Trans. Electron Dev., 1998, 45, 2505–2513.