A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures-Reference-Cited by-同舟云学术

A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures

Published: Issue: Volume: Page:25-39
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Container-title:Vlsi-Soc: From Systems To Silicon
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Author:

Oliveira Leonardo L.,Santos Cristiano,Ferrão Daniel,Costa Eduardo,Monteiro José,Martins João Baptista,Bampi Sergio,Reis Ricardo

Publisher

Springer US

Link

http://link.springer.com/content/pdf/10.1007/978-0-387-73661-7_3.pdf

Reference18 articles.

1. Callaway, T.; Swartzlander, E. Optimizing multipliers for WSI. In Fifth Annual IEEE International Conference on Wafer Scale Integration, pages 85-94, 1993.

2. Cherkauer, B; Friedman, E. A Hybrid Radix-4/Radix-8 Low Power, High Speed Multiplier Architecture for Wide Bit Widths. In IEEE International Symposium on Circuits and Systems, volume 4, pages 53-56, 1996.

3. Wang, Y.; Jiang, Y.; Sha, E. On Area-Efficient Low Power Array Multipliers. In the 8th IEEE International Conference on Electronics, Circuits and Systems, pages 1429-1432, 2001

4. Costa E. da; Monteiro J., and S. Bampi. A New Architecture for 2's Complement Gray Encoded Array Multiplier. In Proceedings Symposium on Integrated Circuits and Systems, pages 14-19, 2002.

5. Costa, E., Monteiro, J., Bampi, S. A New Architecture for Signed Radix-2m Pure Array Multiplier. IEEE ICCD, September 2002.

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