1. R. Bayardo Jr. and R. Schrag, “Using CSP Look-Back Techniques to Solve Real-World SAT Instances,” National Conference on Artificial Intelligence, pp. 203–208, 1997.
2. F. Brglez and H. Fujiwara, “A Neutral List of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN,” International Symposium on Circuits and Systems, 1985.
3. J. L. Carter, V. S. Iyengar and B. K. Rosen, “Efficient Test Coverage Determination for Delay Faults,” International Test Conference, pp. 418–427, September, 1987.
4. C. -A. Chen and S. K. Gupta, “A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuits,” Design Automation Conference, pp. 209–214, 1996.
5. K. -T. Cheng and H. -C. Chen, “Delay Testing For Non-Robust Untestable Circuits,” International Test Conference, pp. 954–961, 1993.