1. Dual-Rail Precharge Logic-Based Side-Channel Countermeasure for DNN Systolic Array;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-09
2. Another Look at Side-Channel-Resistant Encoding Schemes;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08
3. Breaching the Gap: Modelling SRAM-PUFs via Side-Channel Signatures;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12
4. Improved Fault Analysis on Subterranean 2.0;IEEE Transactions on Computers;2024-06
5. Measured Traces Reduction Using SNR of Leakage for Tolerance Evaluation to Deep Learning-based Side-channel Attack;2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa);2024-05-20