Hardware Synthesis from Protocol Specifications in LOTOS-Reference-Cited by-同舟云学术

Hardware Synthesis from Protocol Specifications in LOTOS

Published:1998 Issue: Volume: Page:405-420
ISSN:1868-4238
Container-title:IFIP Advances in Information and Communication Technology
language:
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Author:

Yasumoto Keiichi,Kitajima Akira,Higashino Teruo,Taniguchi Kenichi

Publisher

Springer US

Link

http://link.springer.com/content/pdf/10.1007/978-0-387-35394-4_25

Reference16 articles.

1. Faci, M. and Logrippo, L.: “Specifying Hardware Systems in LOTOS”, Proc. IFIP Int. Conf on Hardware Description Languages and Applications (CHDL’93): 305–312 (1993).

2. Higashino, T., Yasumoto, K., Kitamichi, J. and Taniguchi, K.: “Hardware Synthesis from a Restricted Class of LOTOS Expressions”, Proc. 14th IFIP Int. Symp. on Protocol Specification, Testing, and Verification (PSTV-XIV): 355–362 (1994).

3. ISO: “Information Processing System, Open Systems Interconnection, LOTOS - A Formal Description Technique Based on the Temporal Ordering of Observational Behaviour”, ISO 8807 (1989).

4. ISO/IEC/TR 10167: “Information Technology — Open Systems Interconnection — Guidelines for the application of Estelle, LOTOS and SDL” (1991).

5. Kitajima, A., Yasumoto, K., Higashino, T. and Taniguchi, K.: “A Method to Convert Concurrent EFSMs with Multi-Rendezvous into Synchronous Sequential Circuits”, IEICE Trans. on Fundamentals, E81-A (4): 566–575 (1998).

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