Application-Specific Multi-Threaded Dynamic Memory Management
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Publisher
Springer New York
Link
http://link.springer.com/content/pdf/10.1007/978-1-4419-6778-7_2.pdf
Reference26 articles.
1. S. Agarwala et al. A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure. In Proc. of ISSCC, pages 262–601. IEEE Press, 2007.
2. D. Atienza et al. Systematic Dynamic Memory Management Design Methodology for Reduced Memory Footprint. ACM Trans. Des. Autom. Electron. Syst. (TODAES), 11(2):465–489, Apr. 2006.
3. A. Bartzas et al. Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information. In Proc. of ASP-DAC, pages 434–439, 2008.
4. E. Berger et al. Hoard: A scalable memory allocator for multithreaded applications. SIGPLAN Not, 35(11), Nov. 2000.
5. Emery D. Berger, Benjamin G. Zorn, and Kathryn S. McKinley. Composing high-performance memory allocators. In In Proceedings of the 2001 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI, pages 114–124, 2001.
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