Design of Application-Specific 3D Networks-on-Chip Architectures-Reference-Cited by-同舟云学术

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Design of Application-Specific 3D Networks-on-Chip Architectures

Published:2010-11-06 Issue: Volume: Page:167-191
ISSN:1558-9412
Container-title:Integrated Circuits and Systems
language:
Short-container-title:

Author:

Yan Shan,Lin Bill

Publisher

Springer New York

Link

http://link.springer.com/content/pdf/10.1007/978-1-4419-7618-5_8

Reference48 articles.

1. W. J. Dally, B. Towles, “Route packet, not wires: On-chip interconnection networks,” DAC, 2001.

2. L. Benini, G. De Micheli, “Networks on chips: A new SoC paradigm,” IEEE Computer, vol. 35, no. 1, pp. 70–78, Jan. 2002.

3. M. B. Taylor et al., “The RAW microprocessor: A computational fabric for software circuits and general-purpose programs,” IEEE Micro, vol. 22, no. 6, pp. 25–35, Mar./Apr. 2002.

4. K. Sankaralingam et al., “Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture,” ISCA, 2003.

5. J. Hu, R. Marculescu, “Energy-aware mapping for tile-based NoC architectures under performance constraints,” ASP-DAC, 2003.

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Qualitative Analysis of 3D Routing Algorithms in 3×3×3 Mesh NoC Topology Under Varying Load in Bio-SoC;International Journal of E-Health and Medical Communications;2020-07

2. Reliable routing schemes in 3D network on chip;International Journal of Embedded Systems;2020

3. REDELF;ACM Journal on Emerging Technologies in Computing Systems;2015-09-21

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