Author:
Sen Shreyas,Natarajan Vishwanath,Chatterjee Abhijit
Reference54 articles.
1. http://cseweb.ucsd.edu/classes/wi10/cse241a/slides/Ch1_Introduction.pptx
2. Borkar S, Karnik T, De V (2004) Design and reliability challenges in nanometer technologies, DAC ’04, p. 75
3. The international technology roadmap for semiconductors ITRS WEBSITE. [Online]. Available: http://public.itrs.net/Links/2009ITRS/2009Chapters_2009Tables/2009_Yield.pdf (accessed 4/12/2010)
4. Mukhopadhyay S, Kim K, Mahmoodi H, Roy K (Jun 2007) Design of a process variation tolerant self-repairing SRAM for yield enhancement in nanoscaled CMOS. IEEE J Solid-State Circuits 42(6):1370–1382
5. Azizi N, Khellah MM, De V, Najm FN (2005) Variations-aware low-power design with voltage scaling. DAC’ 05, pp 529–534
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