1. S. Tam, S. Rusu, U. Nagarji Desai, R. Kim, J. Zhang, and I. Young, “Clock generation and distribution for the first IA-64 microprocessor,” IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1545–1552, Nov. 2000.
2. T. Xanthopoulos, D. W. Bailey, A. K. Gangwar, M. K. Gowan, A. K. Jain, and B. K. Prewitt, “The design and analysis of the clock distribution network for a 1.2 GHz Alpha microprocessor,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2001), 2001, pp. 402–403.
3. P. J. Restle, T. G. McNamara, D. A. Webber, P. J. Camporese, K. F. Eng, K. A. Jenkins, D. H. Allen, M. J. Rohn, M. P. Quaranta, D. W. Boerstler, C. J. Alpert, C. A. Carter, R. N. Bailey, J. G. Petrovick, B. L. Krauter, and B. D. McCredie, “A clock distribution network for microprocessors,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 792–799, May 2001.
4. P. J. Restle, C. A. Carter, J. P. Eckhardt, B. L. Krauter, B. D. McCredie, K. A. Jenkins, A. J. Weger, and A. V. Mule, “The clock distribution of the Power4 microprocessor,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2002), vol. 1, 2002, pp. 144–145.
5. N. Bindal, T. Kelly, N. Velastegui, and K. L. Wong, “Scalable sub-10ps skew global clock distribution for a 90nm multi-GHz IA microprocessor,” in Digest of Technical Papers IEEE International Solid-State Circuits Conference (ISSCC 2003), 2003, pp. 346–347,498.