Author:
Jayakumar Nikhil,Paul Suganth,Garg Rajesh,Gulati Kanupriya,Khatri Sunil P.
Reference17 articles.
1. Calhoun, B.H., Wang, A., Chandrakasan, A., Kosonocky, S.: Device Sizing for Minimum Energy Operation in Subthreshold Circuits. In: Proc. IEEE Custom Integrated Circuits Conference, pp. 95–98. Orlando, FL (2004)
2. Cao, Y., Sato, T., Sylvester, D., Orshansky, M., Hu, C.: New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design. In: Proc. IEEE Custom Integrated Circuit Conference, pp. 201–204. Orlando, FL (2000). http://www-device.eecs.berkeley.edu/~ptm
3. Gonzalez, R., Gordon, B.M., Horowitz, M.A.: Supply and Threshold Voltage Scaling for Low Power CMOS. IEEE Journal of Solid-State Circuits 32(8), 1210–1216 (1997)
4. Jayakumar, N., Khatri, S.: A METAL and VIA Maskset Programmable VLSI Design Methodology Using PLAs. In: Proc. IEEE/ACM International Conference on Computer Aided Design, pp. 590–594. San Jose, CA (2004)
5. Khatri, S., Mehrotra, A., Brayton, R., Sangiovanni-Vincentelli, A., Otten, R.: A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. In: Proc. Design Automation Conference. New Orleans, LA (1999)