Author:
Jayakumar Nikhil,Paul Suganth,Garg Rajesh,Gulati Kanupriya,Khatri Sunil P.
Reference12 articles.
1. Aguiav, R.L., Santos, D.M.: Modelling Charge-Pump Delay Locked Loops. In: Proc. International Conference on Electronics, Circuits and Systems, pp. 823–826. Pafos, Cyprus (1999)
2. Cao, Y., Sato, T., Sylvester, D., Orshansky, M., Hu, C.: New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design. In: Proc. IEEE Custom Integrated Circuit Conference, pp. 201–204. Orlando, FL (2000). http://www-device.eecs.berkeley.edu/~ptm
3. Jayakumar, N., Khatri, S.: A METAL and VIA Maskset Programmable VLSI Design Methodology Using PLAs. In: Proc. IEEE/ACM International Conference on Computer Aided Design, pp. 590–594. San Jose, CA (2004)
4. Khatri, S., Mehrotra, A., Brayton, R., Sangiovanni-Vincentelli, A., Otten, R.: A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. In: Proc. Design Automation Conference. New Orleans, LA (1999)
5. Khatri, S.P., Brayton, R.K., Sangiovanni-Vincentelli, A.: Cross-talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. In: Proc. IEEE/ACM International Conference on Computer Aided Design, pp. 412–418. San Jose, CA (2000)