Co-optimization of Power, Thermal, and Signal Interconnect for 3D ICs

Author:

Lee Young-Joon,Healy Michael,Lim Sung Kyu

Publisher

Springer US

Reference25 articles.

1. Shahidi GG (2007) Evolution of CMOS technology at 32nm and beyond. In: Proceedings of the IEEE custom integrated circuits conference, pp 413–416

2. Bakir M, Dang B, Meindl J (2007) Revolutionary nanosilicon ancillary technologies for ultimate-performance gigascale systems. In: Proceedings of the IEEE custom integrated circuits conference, pp 421–428

3. Joyner JW, Zarkesh-Ha P, Meindl JD (2004) Global interconnect design in a three-dimensional system-on-a-chip. IEEE Trans VLSI Syst 12(2):367–371 AQ: Please check if the inserted volume number “12” is appropriate in reference [Joyner et al., 2004].

4. King CK, Sekar D, Bakir MS, Dang B, Pikarsky J, Meindl JD (2008) 3D stacking of chips with electrical and microfluidic I/O interconnects. In: Proceedings of the electronics components and technology conference

5. Sekar D, King C, Dang B, Spencer T, Thacker H, Joseph P, Bakir MS, Meindl JD (2008) A 3D-IC technology with integrated microchannel cooling. In: Proceedings of the international interconnect technology conference

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