1. Naveh Y, Rimon M, Jaeger I, Katz Y, Vinov M, Marcus E, Shurek G (2007) Constraint-based random stimuli generation for hardware verification. AI Mag 28:13–30
2. Moss A (2007) Constraint patterns and search procedures for CP-based random test generation. In: Haifa verification conference, pp 86–103
3. Cadence web page (2007) Incisive Enterprise Specman Products.
http://www.cadence.com/rl/
Resources/datasheets/specman_elite_ds_OnlinePDF.pdf; We are not aware of an academic publication of Cadence’s constraint solver
4. Iyer MA (2003) Race a word-level ATPG-based constraints solver system for smart random simulation. In: Proceedings of the international test conference, 2003, (ITC’03), pp 299–308
5. Chandra AK, Iyengar VS (1992) Constraint solving for test case generation: a technique for high-level design verification. In: Proceedings of IEEE international conference on computer design: VLSI in computers and processors, ICCD’92, pp 245–248