1. R. Abbott, K. Kokkonen, R.I. Kung and R.J. Smith, ?Equipping a Line of Memories with Spare Cells,? Electronics, pp. 127?130, July 28, 19814.
2. B. Ciciani and G. Iazeolla, ?A Straightforward Yield Model for Fault-Tolerant VLSI Memory Chips?, IFIP TC-10 Conference on ?Design Methodology in VLSI and computer architecture,? Sept. 1988, Pisa, Italy.
3. B. Ciciani and G. Iazeolla, ?A Yield Model for the Evaluation of Topologically Constrained Chip Architectures,? IEEE Int. Conf. on Computer Design (ICCD), Cambridge, MA, Oct. 1989.
4. B. Ciciani and G. Iazeolla, ?A Markov-chain Based Yield Model for VLSI Fault Tolerant Chips,? IEEE Transactions on Computer-Aided Design, 10 (2): 252?259, Feb. 1991.
5. J.A.B. Fortes and C.S. Raghavendra, ?Gracefully Degradable Processor Arrays,? IEEE Trans. on Computers, C-34 (11): 1033?1043, Nov. 1985.