FIT-IT-Projekt DARTS: dezentrale fehlertolerante Taktgenerierung

Author:

Schmid U.,Steininger A.,Sust M.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Reference27 articles.

1. Bhamidipati, R., Zaidi, A., Makineni, S., Low, K. K., Chen, R., Liu, K.-Y., Dalgrehn, J. (2002): Challenges and methodologies for implementing high-performance network processors. Intel Technology Journal. Intel Corp., Vol. 6, Issue 3, August 15, 2002.

2. Chapiro, D. M. (1984): Globally-asynchronous locally-synchronous systems. Ph.D. thesis, Stanford University, Oct. 1984.

3. Chelcea, T., Novick, S. M. (2000): A low-latency FIFO for mixed-clock systems. IEEE Computer Society Press: IEEE Computer Society Workshop on VLSI, April 2000: 119–126.

4. Choi, B.-R., Ho Park, K., Kim, M. (1990): An improved hardware implementation of the fault-tolerant clock synchronization algorithm for large multiprocessor systems. IEEE Computer Society Press: IEEE Transactions on Comp., Vol. 39, No. 3, March 1990: 404–407.

5. Constantinescu, C. (2002): Impact of deep submicon technology on dependability of VLSI circuits. IEEE Computer Society Press: Proc. of the Int. Conf. on Dependable Systems and Networks (DSN) 2002, June 2002: 205–209.

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