A new universal gate for low power SoC applications

Author:

GEETHA PRIYA M,BASKARAN K

Publisher

Springer Science and Business Media LLC

Subject

Multidisciplinary

Reference10 articles.

1. Baskaran K, Geetha Priya M and Krishnaveni D 2011 Leakage power reduction techniques in deep submicron technologies for VLSI applications. Proceedings of International Conference on Communication Technology and System Design, Elsevier- Procedia Engineering, 30:1163–1170

2. Franco Maloberti 2001 Analog design for CMOS VLSI systems. The Netherlands: Kluwer Academic Publishers

3. Geetha Priya M, Baskaran K, Krishnaveni D and Srinivasan S 2012 A new leakage power reduction technique for CMOS VLSI circuits. Journal of Artificial Intelligence, 5: 227–232

4. Goel Sumeer, Ashok Kumar and Magdy A Bayoumi 2006 Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style. IEEE Transactions on VLSI Systems, 14: 1309–1321

5. Koomey Jonathan, Berard Stephen, Sanchez Marla and Wong Henry 2011 Implications of historical trends in the electrical efficiency of computing. Annals of the History of Computing, IEEE, 33: 46–54

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1. Design and Evaluation of Low Power 2 to 4 Decoder Circuit Using Three and Four Transistors NAND Gates;2024 International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S);2024-06-08

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