Design of 4-bit ALU using sub-threshold adiabatic logic (SAL)
Author:
Publisher
Springer Science and Business Media LLC
Subject
Multidisciplinary
Link
https://link.springer.com/content/pdf/10.1007/s12046-021-01668-3.pdf
Reference11 articles.
1. M Chanda, S Jain, D Swapnadip and CK Sarkar 2015 “Implementation of sub-threshold adiabatic logic for ultralow-power application”. IEEE Trans. VLSI Syst. 23(12): 2782–2790
2. Chaudhuri A, Saha M, Bhowmik M, Pradhan S N and Das S 2015 Implementation of circuit in different adiabatic logic. In: Proceedings of the 2nd International Conference on Electronics and Communication Systems (ICECS), pp. 353–359
3. Kalyani P, Kumar P S and Sekhar P C 2016 Energy efficient logic gates using sub-threshold adiabatic logic. In: Proceedings of the International Conference on Inventive Computation Technologies (ICICT), pp. 1–6
4. Yadav R K, Rana A K, Chauhan S, Ranka D and Yadav K 2011 Four phase clocking rule for energy efficient digital circuits: an adiabatic concept. In: Proceedings of the 2nd International Conference on Computer and Communication Technology, pp. 209–214
5. Ranjith K G, Chavan A K P and Aradhya H V R 2017 Sub-threshold adiabatic logic (SAL) based building blocks for combinational system design. In: Proceedings of the 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), pp. 96–100
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