Design, development and testing of a 16-bit reduced instruction set computer architecture based processor
Author:
Publisher
Springer Science and Business Media LLC
Subject
Multidisciplinary
Link
https://link.springer.com/content/pdf/10.1007/s12046-023-02304-y.pdf
Reference8 articles.
1. Galani Tina G, Saini R and Daruwala R 2013 Design and implementation of 32-bit RISC processor using Xilinx. Int. J. Emerg. trends Electr. Electron. 5: 18–24
2. Rao K V, Angeline A A and Bhaaskaran V S K 2015 Design of a 16 bit RISC processor. Indian J Sci Technol. 8: 1–7
3. Trivedi P and Tripathi R 2015 Design & analysis of 16 bit RISC processor using low power pipelining. In: Proceeding of International Conference On Computing, Communication & Automation, pp. 1294–1297
4. Sakthikumaran S S and Bhaaskaran V 2011 16-Bit RISC processor design for convolution application. In: Proceeding of International Conference on Recent Trends In Information Technology (ICRTIT). pp. 394–397
5. Bhagat S and Bhandari S 2018 Design and analysis of 16-bit RISC processor. In: Proceeding of Fourth International Conference On Computing Communication Control And Automation (ICCUBEA). pp. 1–4
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