Language and Hardware Acceleration Backend for Graph Processing-Reference-Cited by-同舟云学术

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Language and Hardware Acceleration Backend for Graph Processing

Published:2018-12-20 Issue: Volume: Page:71-88
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
language:
Short-container-title:

Author:

Mokhov Andrey,Gennaro Alessandro de,Tarawneh Ghaith,Wray Jonny,Lukyanov Georgy,Mileiko Sergey,Scott Joe,Yakovlev Alex,Brown Andrew

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-030-02215-0_4

Reference27 articles.

1. R. Albert, A.-L. Barabási, Statistical mechanics of complex networks. Rev. Mod. Phys. 74(1), 47 (2002)

2. T.H. Cormen, C.E. Leiserson, R.L. Rivest, C. Stein, Introduction to Algorithms (MIT Press, London/Cambridge, 2001)

3. B. Betkaoui, D.B. Thomas, W. Luk, N. Przulj, A framework for FPGA acceleration of large graph problems: Graphlet counting case study. In International Conference on Field-Programmable Technology, New Delhi (2011)

4. E. Nurvitadhi, G. Weisz, Y. Wang, S. Hurkat, M. Nguyen, J.C. Hoe, J.F. Martínez, C. Guestrin, Graphgen: an FPGA framework for vertex-centric graph computation. In International Symposium on Field-Programmable Custom Computing Machines (IEEE, Piscataway, 2014), pp. 25–28

5. N. Kapre, Custom FPGA-based soft-processors for sparse graph acceleration. In International Conference on Application-Specific Systems, Architectures and Processors (IEEE, 2015), pp. 9–16

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Synchronization in graph analysis algorithms on the Partially Ordered Event‐Triggered Systems many‐core architecture;IET Computers & Digital Techniques;2022-03

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