Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs

Author:

Copetti Thiago S.,Medeiros Guilherme C.,Poehls Letícia M. B.,Balen Tiago R.

Publisher

Springer International Publishing

Reference39 articles.

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2. Intel: Intel® 22 nm Technology. http://www.intel.com/content/www/us/en/silicon-innovations/intel-22nm-technology.html

3. Samsung: Strong 14 nm FinFET Logic Process and Design Infrastructure for Advanced Mobile SOC Applications (2013)

4. Tang, S.H., et al.: FinFET-a quasi-planar double-gate MOSFET. In: 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), pp. 118–119. IEEE (2001)

5. Yu, B., et al.: FinFET scaling to 10 nm gate length. In: Digest. International Electron Devices Meeting, pp. 251–254. IEEE (2002)

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects;Journal of Electronic Testing;2021-06

2. Hard-to-Detect Fault Analysis in FinFET SRAMs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-06

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