Author:
Agarwal Sukarn,Kapoor Hemangee K.
Publisher
Springer International Publishing
Reference23 articles.
1. Binkert, N., et al.: The gem5 simulator. SIGARCH Comput. Archit. News 39(2), 1–7 (2011)
2. Dong, X., Xu, C., Xie, Y., Jouppi, N.P.: NVSim: a circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 31, 994–1007 (2012)
3. Bienia, C., Kumar, S., Singh, J.P., Li, K.: The PARSEC benchmark suite: characterization and architectural implications. In: International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 72–81 (2008)
4. Apalkov, D., et al.: Spin-transfer torque magnetic random access memory. J. Emerg. Technol. Comput. Syst. 9(2), 13:1–13:35 (2013). Article 13
5. Qureshi, M.K., Gurumurthi, S., Rajendran, B.: Phase Change Memory: From Devices to Systems, 1st edn. Morgan & Claypool Publishers, San Rafael (2011)
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献