1. A. Althoff, J. Blackstone, R. Kastner, Holistic power side-channel leakage assessment: towards a robust multidimensional metric, in 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (IEEE, Piscataway, 2019), pp. 1–8
2. G. Becker, J. Cooper, E. De Mulder, G. Goodwill, J. Jaffe, G. Kenworthy, Test vector leakage assessment (TVLA) derived test requirements (DTR) with AES, in International Cryptographic Module Conference (2013)
3. S. Bhasin, J.L. Danger, T. Graba, Y. Mathieu, D. Fujimoto, M. Nagata, Physical security evaluation at an early design-phase: a side-channel aware simulation methodology, in Proceedings of International Workshop on Engineering Simulations for Cyber-Physical Systems (2013), pp. 13–20
4. E. Brier, C. Clavier, F. Olivier, Correlation power analysis with a leakage model, in International Workshop on Cryptographic Hardware and Embedded Systems (Springer, Berlin, 2004), pp. 16–29
5. M. Bucci, R. Luzzi, F. Menichelli, R. Menicocci, M. Olivieri, A. Trifiletti, Testing power-analysis attack susceptibility in register-transfer level designs. IET Inform. Secur. 1(3), 128–133 (2007)