1. Bennett P (2004) The why, where and what of low-power SoC design//EEdesign.com.
http://www.eetimes.com/document.asp?doc_id=1276973
2. Manke JW, Kerlick GD, Levine D, Banerjee S, Dillon E (2001) Parallel performance of two applications in the Boeing high performance computing benchmark suite. Parallel Comput 27:457–475
3. Lookin NA, oth (2007) VLSI based on two-dimensional reconfigurable array of processor elements and their implementation for numerical algorithms in real-time systems. Proceedings of IP based electronics system, 2007. Espace Congrés du World Trade Center 5 place Robert Schuman, 38500 Grenoble, France, pp 541–546
4. Lookin NA (2004) Reconfigurable processor arrays for real-time systems: architectures, efficiency, application. Proceedings of international science school high-performance computer systems, Taganrog, Russia, pp 44–59
5. Prangishvili IV, oth (1967) Microelectronics and homogenous structures for logical and computational devices, [in Russian]—science. Moscow