A Versatile and Unified HQC Hardware Accelerator
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-61489-7_17
Reference7 articles.
1. Aguilar Melchor, C., et al.: Towards automating cryptographic hardware implementations: a case study of HQC. In: Deneuville, J.C. (ed.) CBCrypto 2022. LCNS, vol. 13839, pp. 62–76. Springer, Cham (2022). https://doi.org/10.1007/978-3-031-29689-5_4
2. Aguilar Melchor, C., et al.: HQC documentation (2023). http://pqc-hqc.org/doc/hqc-specification_2023-04-30.pdf
3. Antognazza, F., Barenghi, A., Pelosi, G., Susella, R.: A flexible ASIC-oriented design for a full NTRU accelerator. In: Takahashi, A. (ed.) Proceedings of the 28th Asia and South Pacific Design Automation Conference, ASPDAC 2023, Tokyo, Japan, 16–19 January 2023, pp. 591–597. ACM (2023). https://doi.org/10.1145/3566097.3567916
4. Antognazza, F., Barenghi, A., Pelosi, G., Susella, R.: An efficient unified architecture for polynomial multiplications in lattice-based cryptoschemes. In: Mori, P., Lenzini, G., Furnell, S. (eds.) Proceedings of the 9th International Conference on Information Systems Security and Privacy, ICISSP 2023, Lisbon, Portugal, 22–24 February 2023, pp. 81–88. SciTePress (2023). https://doi.org/10.5220/0011654200003405
5. Antognazza, F., Barenghi, A., Pelosi, G., Susella, R.: Performance and efficiency exploration of hardware polynomial multipliers for post-quantum lattice-based cryptosystems. SN Comput. Sci. 5(212) (2024). https://doi.org/10.1007/s42979-023-02547-w
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