1. J.H. Ahn, S.Li, O. Seongil, N. Jouppi, McSimA+ : a manycore simulator with application-level+ simulation and detailed microarchitecture modeling, in 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) (IEEE, Piscataway, 2013), pp. 74–85
2. H. Amrouch, V.M. van Santen, T. Ebi, V. Wenzel, J. Henkel, Towards interdependencies of aging mechanisms, in 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), (IEEE, Piscataway, 2014), pp. 478–485
3. M. Berktold, T. Tian, CPU monitoring with DTS/PECI, 2010. http://www.intel.com/content/www/us/en/embedded/testing-and-validation/cpu-monitoring-dts-peci-paper.html
4. C. Bienia, S. Kumar, J.P. Singh, K. Li, The parsec benchmark suite: characterization and architectural implications, in Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, PACT ’08 (ACM, New York, 2008), pp. 72–81. http://doi.acm.org/10.1145/1454115.1454128
5. N. Binkert, B. Beckmann, G. Black, S.K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D.R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M.D. Hill, D.A. Wood, The gem5 simulator. SIGARCH Comput. Archit. News 39(2), 1–7 (2011). http://doi.acm.org/10.1145/2024716.2024718