1. D. Angot, V. Huard, L. Rahhal, A. Cros, X. Federspiel, A. Bajolet, Y. Carminati, M. Saliva, E. Pion, F. Cacho et al., BTI variability fundamental understandings and impact on digital logic by the use of extensive dataset, in Proceedings of the IEEE International Electron Devices Meeting (IEDM), (IEEE, Piscataway, 2013), pp. 15–4
2. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, S. Vrudhula, Predictive modeling of the NBTI effect for reliable design, in IEEE Custom Integrated Circuits Conference (IEEE, Piscataway, 2006), pp. 189–192
3. J. Bhaskarr Velamala, K.B. Sutaria, H. Shimizu, H. Awano, T. Sato, G. Wirth, Y. Cao, Compact modeling of statistical BTI under trapping/detrapping. IEEE Trans. Electron Devices 60(11), 3645–3654 (2013)
4. V.V. Camargo, B. Kaczer, G. Wirth, T. Grasser, G. Groeseneken, Use of SSTA tools for evaluating BTI impact on combinational circuits. IEEE Trans. Very Large Scale Integr. VLSI Syst. 22(2), 280–285 (2014)
5. B. Kaczer, S. Mahato, V. V. de Almeida Camargo, M. Toledano-Luque, P.J. Roussel, T. Grasser, F. Catthoor, P. Dobrovolny, P. Zuber, G. Wirth et al., Atomistic approach to variability of bias-temperature instability in circuit simulations, in 2011 IEEE International Reliability Physics Symposium (IRPS) (IEEE, Piscataway, 2011), pp. XT–3