Enabling Trust for Advanced Semiconductor Solutions Based on Physical Layout Verification-Reference-Cited by-同舟云学术

Enabling Trust for Advanced Semiconductor Solutions Based on Physical Layout Verification

Published:2020-12-11 Issue: Volume: Page:87-103
ISSN:2196-5544
Container-title:Lecture Notes in Mobility
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Author:

Ludwig Matthias,Lippmann Bernhard,Unverricht Niklas

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-030-65871-7_7

Reference26 articles.

1. McKeefry, H.L.: Industry Counterfeits Costing Semiconductor Industry Billions (2019). https://www.eetasia.com/news/article/Counterfeits-Costing-Semiconductor-Industry-Billions

2. Klar, J.: Counterfeits Plague Electronics (2017). https://www.eetasia.com/news/article/counterfeits-plague-electronics-industry

3. Semiconductor Industry Association: Winning the battle against counterfeit semiconductor products (2013)

4. Hunt, G , Letey, G., Nightingale, E.B.: The seven properties of highly secure devices. In: Microsoft Research NExT Operating Systems Technologies Group (2017)

5. Laackmann, P., Janke, M.: Hardware-Trojaner in Security-Chips - Eine Reise auf die dunkle Seite (2015). https://media.ccc.de/v/32c3-7146-hardware-trojaner_in_security-chips”

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. ViTaL: Verifying Trojan-Free Physical Layouts through Hardware Reverse Engineering;2021 IEEE Physical Assurance and Inspection of Electronics (PAINE);2021-11-30

2. CRESS: Framework for Vulnerability Assessment of Attack Scenarios in Hardware Reverse Engineering;2021 IEEE Physical Assurance and Inspection of Electronics (PAINE);2021-11-30