Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC
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Springer Nature Switzerland
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https://link.springer.com/content/pdf/10.1007/978-3-031-42921-7_15
Reference20 articles.
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2. Amorim, R.C., Martins, R., Harikrishnan, P., Ghiglione, M., Helfers, T.: Dependable MPSoC framework for mixed criticality applications. In: European Workshop on On-Board Data Processing (OBDP) (2021). https://doi.org/10.5281/zenodo.5521521
3. Aranda, L.A., Ruano, O., Garcia-Herrero, F., Maestro, J.A.: ACME-2: improving the extraction of essential bits in Xilinx SRAM-based FPGAs. IEEE Trans. Circuits Syst. II Express Briefs 69(3), 1577–1581 (2022). https://doi.org/10.1109/TCSII.2021.3105558
4. Aranda, L.A., Sánchez-Macián, A., Maestro, J.A.: ACME: A tool to improve configuration memory fault injection in SRAM-based FPGAs. IEEE Access 7, 128153–128161 (2019). https://doi.org/10.1109/ACCESS.2019.2939858
5. Berg, M., et al.: Effectiveness of internal vs. external SEU scrubbing mitigation strategies in a Xilinx FPGA: Design, test, and analysis. In: European Conference on Radiation and Its Effects on Components and Systems (RADECS), pp. 1–8 (2007). https://doi.org/10.1109/RADECS.2007.5205603
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