Software and Hardware Co-design for Low-Power HPC Platforms

Author:

Ploumidis Manolis,Kallimanis Nikolaos D.,Asiminakis Marios,Chrysos Nikos,Xirouchakis Pantelis,Gianoudis Michalis,Tzanakis Leandros,Dimou Nikolaos,Psistakis Antonis,Peristerakis Panagiotis,Kalokairinos Giorgos,Papaefstathiou Vassilis,Katevenis Manolis

Publisher

Springer International Publishing

Reference17 articles.

1. LAMMPS Molecular Dynamics Simulator. Sandia National Laboratories. https://lammps.sandia.gov

2. The ExaNest project. European Exascale System Interconnect and Storage. GA-671553. www.exanest.eu

3. Alverson, B., Froese, E., Kaplan, L., Roweth, D.: Cray xc series network. Cray Inc., White Paper WP-Aries01-1112 (2012)

4. Ammendola, R., et al.: Apenet: a high speed, low latency 3d interconnect network. In: cluster, p. 481. Citeseer (2004)

5. EuroEXA: European Exascale System Interconnect and Storage. https://euroexa.eu/

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1. Low-latency Communication in RISC-V Clusters;Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region;2024-01-18

2. Optimized Page Fault Handling During RDMA;IEEE Transactions on Parallel and Distributed Systems;2022-12-01

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