Recycled FPGA Detection
Author:
Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-31034-8_4
Reference21 articles.
1. Alam, M.M., Tehranipoor, M., Forte, D.: Recycled FPGA detection using exhaustive LUT path delay characterization and voltage scaling. IEEE Trans. Very Large Scale Integr. Syst. 27(12), 2897–2910 (2019). https://doi.org/10.1109/TVLSI.2019.2933278
2. Amouri, A., Tahoori, M.: A low-cost sensor for aging and late transitions detection in modern FPGAs. In: 2011 21st International Conference on Field Programmable Logic and Applications, pp. 329–335 (2011). https://doi.org/10.1109/FPL.2011.66
3. Anandakumar, N.N., Hashmi, M.S., Sanadhya, S.K.: Design and analysis of FPGA based PUFs with enhanced performance for hardware-oriented security. ACM J. Emerg. Technol. Comput. Syst. 18(4), 1–26 (2022)
4. Anandakumar, N.N., Sanadhya, S.K., Hashmi, M.S.: Design, implementation and analysis of efficient hardware-based security primitives. In: 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), pp. 198–199. IEEE, Piscataway (2020)
5. Bergman, T.D., Manager, C.P., Liszewski, K.T.: Battelle barricade: a nondestructive electronic component authentication and counterfeit detection technology. In: 2016 IEEE Symposium on Technologies for Homeland Security (HST), pp. 1–6 (2016). https://doi.org/10.1109/THS.2016.7568901
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