Recycled Chip Detection Using RO-Based Odometer
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Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-31034-8_3
Reference46 articles.
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2. Alam, M.M., Tehranipoor, M., Forte, D.: Recycled FPGA detection using exhaustive LUT path delay characterization and voltage scaling. IEEE Trans. Very Large Scale Integr. Syst. 27(12), 2897–2910 (2019)
3. Anandakumar, N.N., Sanadhya, S.K., Hashmi, M.S.: Design, implementation and analysis of efficient hardware-based security primitives. In: 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), pp. 198–199. IEEE, Piscataway (2020)
4. Anandakumar, N.N., Hashmi, M.S., Tehranipoor, M.: FPGA-based physical unclonable functions: a comprehensive overview of theory and architectures. Integration 81, 175–194 (2021)
5. Anandakumar, N.N., Hashmi, M.S., Chaudhary, M.A.: Implementation of efficient XOR arbiter PUF on FPGA with enhanced uniqueness and security. IEEE Access 10, 129832–129842 (2022)
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