Author:
Gomony Manil Dev,Jivanescu Mihaela,Olaziregi Nikolas
Publisher
Springer Nature Switzerland
Reference15 articles.
1. Cadence Design Systems Inc.: Tensilica customizable processors (2019). https://ip.cadence.com/ipportfolio/tensilica-ip/xtensa-customizable
2. Codasip Ltd.: Codasip Studio (2019). https://www.codasip.com/custom-processor/
3. Eusse, J., Williams, C., Leupers, R.: CoEx: a novel profiling-based algorithm/architecture co-exploration for ASIP design. In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), pp. 1–8 (2013). https://doi.org/10.1109/ReCoSoC.2013.6581520
4. Eusse, J., et al.: Pre-architectural performance estimation for ASIP design based on abstract processor models. In: 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), pp. 133–140 (2014). https://doi.org/10.1109/SAMOS.2014.6893204
5. Hoare, R.R., et al.: Rapid VLIW processor customization for signal processing applications using combinational hardware functions. EURASIP J. Adv. Signal Process. 2006(1), 1–23 (2006). https://doi.org/10.1155/ASP/2006/46472
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