Author:
Levi Itamar,Fish Alexander
Publisher
Springer International Publishing
Reference33 articles.
1. W. Kim, M.S. Gupta, G.-Y. Wei, D. Brooks, System level analysis of fast, per-core DVFS using on-chip switching regulators, in 2008 IEEE 14th International Symposium on High Performance Computer Architecture (IEEE, Piscataway, 2008), pp. 123–134
2. B.R. Zeydel, D. Baran, V.G. Oklobdzija, Energy-efficient design methodologies: high-performance VLSI adders. IEEE J. Solid State Circuits 45(6), 1220–1233 (2010)
3. H.Q. Dao, B.R. Zeydel, V.G. Oklobdzija, Energy optimization of pipelined digital systems using circuit sizing and supply scaling. IEEE Trans. Very Large Scale Integr. Syst. 14(2), 122 (2006)
4. W. Shen, Y. Cai, X. Hong, J. Hu, An effective gated clock tree design based on activity and register aware placement.IEEE Trans. Very Large Scale Integr. Syst. 18(12), 1639–1648 (2010)
5. J. Shinde, S. Salankar, Clock gating—a power optimizing technique for VLSI circuits, in 2011 Annual IEEE India Conference (IEEE, Piscataway, 2011), pp. 1–4