Author:
Panigrahi Amrit Kumar,Sakshi ,Pradhan Nishant Kumar,Singh Vishakha
Publisher
Springer International Publishing
Reference9 articles.
1. Martha P, Kajal N, Kumari P (2018) An efficient way of implementing high speed 4-bit advanced multipliers in FPGA. IEEE
2. Singh BP, Kumar R (2016) Design and implementation of 8-bit Wallace tree multiplier. 5(4), IIAREEIE
3. Mathew K, Lathe SA (2013) Design and analysis of an array multiplier using an area efficient full adder cell in 32 nm. IJES 2:8–16 CMOS Technology
4. Panigrahi AK, Patra S, Agarwal M, Satapathy S (2019) Design and implementation of a 4 bit high speed ALU using BASYS 3 FPGA kit. In: IPACT 2019 IEEE conference, to appear
5. Panigrahi AK, Ranjan R, Bhoi S, Kumari N (2017) DTMF based home automation system. IJAREEIE, 6(3)