A 0.94 V Dynamic Bias Double Tail Comparator for High-Speed Applications in 5 nm Technology
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-48121-5_10
Reference9 articles.
1. Tang X et al (2020) An energy-efficient comparator with dynamic floating inverter amplifier. IEEE J Solid-State Circ 55(4):1011–1022. https://doi.org/10.1109/JSSC.2019.2960485
2. Pisati M et al (2020) A 243-mW 1.25–56-Gb/s continuous range PAM-4 42.5-dB IL ADC/DAC-based transceiver in 7-nm FinFET. IEEE J Solid-State Circ 55(1):6–18. https://doi.org/10.1109/JSSC.2019.2936307
3. Li S, et al (2020) Low power SAR ADC design with digital background calibration algorithm. Symmetry 12(11):1757. https://doi.org/10.3390/sym12111757
4. Kull L, et al (2013) A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS. In: 2013 IEEE international solid-state circuits conference digest of technical papers, San Francisco, CA, USA, pp 468–469. https://doi.org/10.1109/ISSCC.2013.6487818
5. Bindra HS et al (2022) A 174μVRMS input noise, 1 GS/s comparator in 22nm FDSOI with a dynamic-bias preamplifier using tail charge pump and capacitive neutralization across the latch. IEEE Int Solid-State Circ Conf (ISSCC) 2022:1–3. https://doi.org/10.1109/ISSCC42614.2022.9731728
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