High-Performance Oversampling ADCs
Author:
Publisher
Springer International Publishing
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-22231-3_5
Reference36 articles.
1. Qi, L., Sin, S.-W., Seng-Pan, U., Maloberti, F., & Martins, R. P. (2017). A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH SD modulator with multi-rate opamp sharing. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(10), 2641–2654.
2. Wang, W., Zhu, Y., Chan, C., & Martins, R. P. (2018). A 5.35-mW 10-MHz single-opamp third-order CTΔΣ modulator with CTC opamp and adaptive latch DAC driver in 65-nm CMOS. IEEE Journal of Solid-State Circuits, 53(10), 2783–2794.
3. Song, Y., et al. (2020). A 12.5-MHz bandwidth 77-dB SNDR SAR-assisted noise shaping pipeline ADC. IEEE Journal of Solid-State Circuits, 55(2), 312–321.
4. Zhang, H., Zhu, Y., Chan, C.-H., & Martins, R. P. (2022). An inherent gain error tolerance noise-shaping SAR-assisted pipeline ADC with code-counter-based offset calibration. IEEE Journal of Solid-State Circuits, 57(5), 1480–1491.
5. Zanbaghi, R., Saxena, S., Temes, G., & Fiez, T. S. (2012). A 75-dB SNDR, 5-MHz bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 16mW power. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(8), 1614–1625.
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