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Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction

  • Published:2019 Issue: Volume: Page:166-185
  • ISSN:0302-9743
  • Container-title:Lecture Notes in Computer Science
  • language:
  • Short-container-title:

Author:

Goel Aman,Sakallah Karem

Publisher

Springer International Publishing

Reference51 articles.

1. https://github.com/aman-goel/nfm2019exp

2. ABC: System for Sequential Logic Synthesis and Formal Verification. https://github.com/berkeley-abc/abc

3. The nuXmv model checker. https://nuxmv.fbk.eu

4. Lecture Notes in Computer Science (Lecture Notes in Artificial Intelligence);ZS Andraus,2008

5. Lecture Notes in Computer Science;D Babić,2007

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