1. L. Amarú, P.-E. Gaillardon, G. De Micheli, The EPFL combinational benchmark suite, in International Workshop on Logic and Synthesis (IWLS) (2015)
2. F. Brglez, H. Fujiwara, A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran, in International Symposium on Circuits and Systems (ISCAS) (IEEE Press, 1985), pp. 677–692
3. F. Corno, M.S. Reorda, G. Squillero, RT-level ITC’99 benchmarks and first ATPG results. Des. Test Comput. 17(3), 44–53 (2000)
4. R. Devadoss, K. Paul, M. Balakrishnan, Clocking-based coplanar wire crossing scheme for QCA, in International Conference on VLSI Design (IEEE, 2010), pp. 339–344
5. G. Fontes, P.A.R.L. Silva, J.A.M. Nacif, O.P.V. Neto, R. Ferreira, Placement and routing by overlapping and merging QCA gates, in International Symposium on Circuits and Systems (ISCAS) (IEEE, 2018)