An Overview of Energy-Efficient DNN Training Processors-Reference-Cited by-同舟云学术

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An Overview of Energy-Efficient DNN Training Processors

Published:2023 Issue: Volume: Page:183-210
ISSN:
Container-title:On-Chip Training NPU - Algorithm, Architecture and SoC Design
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Author:

Han Donghyeon,Yoo Hoi-Jun

Publisher

Springer Nature Switzerland

Link

https://link.springer.com/content/pdf/10.1007/978-3-031-34237-0_8

Reference60 articles.

1. D. Shin et al., DNPU: An 8.1TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers (2017), pp. 240–241

2. J. Lee et al., A 21mW low-power recurrent neural network accelerator with quantization tables for embedded deep learning applications, in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC) (2017), pp. 237–240

3. K. Bong et al., A low-power convolutional neural network face recognition processor and a CIS integrated with always-on face detector. IEEE J. Solid-State Circuits 53(1), 115–123 (2018)

4. A. Amravati et al., A 55nm time-domain mixed-signal neuromorphic accelerator with stochastic synapses and embedded reinforcement learning for autonomous micro-robots, in 2018 IEEE International Solid-State Circuits Conference (ISSCC) (2018), pp. 124–126

5. S. Kang et al., B-face: 0.2 MW CNN-based face recognition processor with face alignment for mobile user identification, in 2018 IEEE Symposium on VLSI Circuits (Honolulu, 2018), pp. 137–138

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