Technology Mapping of Logic Functions in LUT Blocks

Author:

Kubica Marcin,Opara Adam,Kania Dariusz

Publisher

Springer International Publishing

Reference24 articles.

1. Chang S, Marek-Sadowska M, Hwang T (1996) Technology mapping for TLU FPGA’s based on decomposition of binary decision diagrams. IEEE Trans Comput-Aided Des 15(10):1226–1235

2. Chávez RS, Rajavel ST, Akoglu A (2012) WL-Emap: Wirelength prediction based technology mapping for FPGAs. In: VIII Southern Conference on Programmable Logic (SPL), pp 1–6

3. Cheng L, Chen D, Wong M, Hutton M, Govig J (2007) Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. IEEE/ACM Int Conf Comput-Aided Des, ICCAD 2007:370–375

4. Cong J, Ding Y (1994) FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 1–12

5. Shen Ch, Lin Z, Fan P, Meng X, Qian W (2016) Parallelizing FPGA technology mapping through partitioning. In: 24th annual international symposium on field-programmable custom computing machines, pp 164–167

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