1. Xilinx, XC3000 Technical Information, xapp024, 1997
2. Xilinx Spartan-3 Generation FPGA User Guide (UG331), 2011
3. Altera (2012) Logic array blocks and adaptive logic modules in Stratix V Devices
4. Anderson J, Wang Q, Ravishankar C (2012) Raising fpga logic density through synthesis-inspired architecture. IEEE Trans Very Large Scale Integr (VLSI) Syst 20(3):537–550
5. Garg V, Chandrasekhar V, Sashikanth M, Kamakoti V (2005) A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. Design automation conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific, vol 2, pp 791–794