Ordering Variables in BDD Diagrams

Author:

Kubica Marcin,Opara Adam,Kania Dariusz

Publisher

Springer International Publishing

Reference22 articles.

1. Chaudhury S, Dutta A (2011) Algorithmic optimization of BDDs and performance evaluation for multi-level logic circuits with area and power trade-offs. Circuits Syst 02:217–224

2. Ebendt R (2003) Reducing the number of variable movements in exact BDD minimization. IEEE Int Symp Circuits Syst (ISCAS) 5:V605–V608

3. Ebendt R, Gunther W, Drechsler R (2004) Combining ordered best-first search with branch and bound for exact BDD minimization. In: Design automation conference 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific, pp 876–879

4. Hong Y, Beerel PA, Burch JR, McMillan KL (2000) Sibling-substitution-based BDD minimization using don’t cares. Trans Comput-Aided Des Integr Circuits Syst 19(1):44–55

5. Gomez-Prado D, Ren Q, Askar S, Ciesielski M, Boutillon E (2004) Variable ordering for Taylor expansion diagrams, High-level design validation and test workshop 2004. Ninth IEEE international high-level design validation and test workshop, pp 55–59

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