Circuit Implementation for High Efficiency
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-030-63944-0_4
Reference50 articles.
1. Neveu, F., et al.: A 100 MHz 91.5% Peak efficiency integrated buck converter with a Three-MOSFET cascode bridge. IEEE Trans. Power Electron. 31(6), 3985–3988 (2016). ISSN: 1941-0107. https://doi.org/10.1109/TPEL.2015.2502058
2. Bezerra, P.A.M., et al.: Analysis and comparative evaluation of stacked-transistor half-bridge topologies implemented with 14 nm bulk CMOS technology. In: 2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL), pp. 1–8 (2017). https://doi.org/10.1109/COMPEL.2017.8013307
3. Kursun, V., et al.: High input voltage step-down DCDC converters for integration in a low voltage CMOS process. In: International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720), pp. 517–521 (2004). https://doi.org/10.1109/ISQED.2004.1283725
4. Kursun, V., et al.: Cascode buffer for monolithic voltage conversion operating at high input supply voltages. In: 2005 IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 464–467 (2005). https://doi.org/10.1109/ISCAS20051464625
5. Burton, E.A., et al.: FIVR – fully integrated voltage regulators on 4th generation intel® core™ SoCs. In: 2014 IEEE Applied Power Electronics Conference and Exposition – APEC 2014, pp. 432–439 (2014). https://doi.org/10.1109/APEC2014.6803344
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