1. N. Agarwal, T. Krishna, L. Peh, N.K. Jha, Garnet: a detailed on-chip network model inside a full-system simulator, in 2009 IEEE International Symposium on Performance Analysis of Systems and Software (2009), pp. 33–42
2. A. Ahmed, F. Farahmandi, Y. Iskander, P. Mishra, Scalable hardware trojan activation by interleaving concrete simulation and symbolic execution, in 2018 IEEE International Test Conference (ITC) (IEEE, Piscataway, 2018), pp. 1–10
3. A. Ahmed, Y. Huang, P. Mishra, Cache reconfiguration using machine learning for vulnerability-aware energy optimization. ACM Trans. Embed. Comput. Syst. 18(2), 1–24 (2019)
4. Alteris FlexNoC Resilience Package, www.arteris.com/flexnoc-resilience-package-functional-safety [Online]
5. D.M. Ancajas, K. Chakraborty, S. Roy, Fort-NoCs: mitigating the threat of a compromised NoC, in 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC) (2014), pp. 1–6