1. 2015 International Technology Roadmap for Semiconductors (ITRS). www.semiconductors.org/main/2015_international_technology_roadmap_for_semiconductors_itrs/
2. A. Agarwal, C. Iskander, R. Shankar, Survey of network on chip (NoC) architectures & contributions. J. Eng. Comput. Archit. 3(1), 21–27 (2009)
3. A. Ahmed, F. Farahmandi, Y. Iskander, P. Mishra, Scalable hardware trojan activation by interleaving concrete simulation and symbolic execution, in 2018 IEEE International Test Conference (ITC) (IEEE, Piscataway, 2018), pp. 1–10
4. A. Ahmed, F. Farahmandi, P. Mishra, Directed test generation using concolic testing on RTL models, in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, pp. 1538–1543
5. A. Ahmed, Y. Huang, P. Mishra, Cache reconfiguration using machine learning for vulnerability-aware energy optimization. ACM Trans. Embed. Comput. Syst. 18(2), 1–24 (2019)