SIRM: Shift Insensitive Racetrack Main Memory

Author:

Zhang Hongbin,Wei Bo,Lu Youyou,Shu Jiwu

Publisher

Springer International Publishing

Reference13 articles.

1. Zhang, C., et al.: Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power. In: Proceedings of the 20th Asia and South Pacific Design Automation Conference, Chiba, Japan, January 2015, pp. 100–105 (2015)

2. Zhang, Y., et al.: Perspectives of racetrack memory for large-capacity on-chip memory: from device to system. IEEE Trans. Circ. Syst. 63(5), 629–638 (2016)

3. Sun, G., et al.: From device to system: cross-layer design exploration of racetrack memory. In: Proceedings of the 18th Design, Automation and Test in Europe (DATE), Grenoble, France, 9–13 March 2015, pp. 1018–1023 (2015)

4. Parkin, S.S., Hayashi, M., Thomas, L.: Magnetic domain-wall racetrack memory. Science 320(5873), 190–194 (2008)

5. Venkatesan R, et al.: TapeCache: a high density, energy efficient cache based on domain wall memory. In: Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 185–190. ACM (2012)

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