A Reconfigurable Arbiter PUF Based on VGSOT MTJ
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-21514-8_27
Reference24 articles.
1. Zhang, D., Zeng, L., Zhang, Y., Klein, J.O., Zhao, W.: Reliability enhanced hybrid CMOS/MTJ logic circuit architecture. IEEE Trans. Mag. 53(11), 1–5 (2017)
2. Bohr, M.T., Young, I.A.: CMOS scaling trends and beyond. IEEE Micro. 37(6), 20–29 (2017)
3. Zhang, D., et al.: Reliability-enhanced separated pre-charge sensing amplifier for hybrid CMOS/MTJ logic circuits. IEEE Trans. Mag. 53(9), 1–5 (2017)
4. Chun, K.C., Zhao, H., Harms, J.D., Kim, T.H., Wang, J.P., Kim, C.H.: A scaling roadmap and performance evaluation in in- plane and perpendicular MTJ based STT-MRAMs for high-density cache memory. IEEE J. Solid State Circuits 48(2), 598–610 (2013)
5. Augustine, C., Mojumder, N., Fong, X., Choday, H., Park, S.P., Roy, K.: STT-MRAMs for future universal memories: Perspective and prospective. In: 28th International Conference on Microelectronics Proceedings, pp. 349–355. IEEE, Nis, Serbia (2012)
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