1. B. Bailey, Power limits of EDA (2016).
http://semiengineering.com/power-limits-of-eda
2. P. Dasgupta, M.K. Srivas, R. Mukherjee, Formal hardware/software co-verification of embedded power controllers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12), 2025–2029 (2014)
3. S. Fine, A. Ziv, Coverage directed test generation for functional verification using bayesian networks, in Proceedings of the 40th annual Design Automation Conference (2003), pp. 286–291
4. K. Grüttner, P.A. Hartmann, K. Hylla, S. Rosinger, W. Nebel, F. Herrera, E. Villar, C. Brandolese, W. Fornaciari, G. Palermo, C. Ykman-Couvreur, D. Quaglia, F. Ferrero, R. Valencia, The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration. MICPRO 37(8, Part C), 966–980 (2013)
5. F. Haedicke, H.M. Le, D. Große, R. Drechsler, CRAVE: an advanced constrained random verification environment for SystemC, in SoC (2012), pp. 1–7