Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms-Reference-Cited by-同舟云学术

Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms

Published:2018 Issue: Volume: Page:153-158
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Yang Zhijie,Wang Lei,Ding Dong,Zhang Xiangyu,Deng Yu,Li Shiming,Dou Qiang

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-030-05677-3_16

Reference9 articles.

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2. Tang, B., S.O. Information, Y.N. University: Case study of the application of field programmable gate array FPGA in the smart skill. Application of IC (2018)

3. Jouppi, N.P., Young, C., Patil, N., Patterson, D., Agrawal, G., Bajwa, R., et al.: In-datacenter performance analysis of a tensor processing unit, pp. 1–12 (2017)

4. Kung, H.T., Leiserson, C.E.: Systolic arrays (for VLSI). In: Proceedings of Sparse Matrix Conference, pp. 256–282 (1978)

5. Farabet, C., Martini, B., Corda, B., Akselrod, P.: NeuFlow: a runtime reconfigurable dataflow processor for vision. In: Computer Vision and Pattern Recognition Workshops, vol. 9, pp. 109–116. IEEE (2011)

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